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WCDMA Quasi-Direct Modulator
with VGA and PA Driver
Table 4. Reference-Divider (RFR) Register
BIT NAME
RFR8 to RFR0
POWER-UP STATE
001010000
BIT LOCATION (0 = LSB)
8 to 0
FUNCTION
Reference-divider register bits
0 0 = Normal operation (lock-detect output at LD pin)
LD1, LD0
00
10, 9
0 1 = RFM-DIV output
1 0 = RFR-DIV output
1 1 = Low logic output
RF CP test bits:
0 0 0 = Normal mode
RCPT2, RCPT1,
RCPT0
000
13, 12, 11
0 0 1 = Source sink ON
0 1 1 = Sink ON
1 0 1 = Source ON
1 1 0 = Source, sink OFF
RESERVED
RESERVED
1
0
14
15
Program to 1 for normal operation
Program to 0 for normal operation
Table 5. Power-Down Modes
POWER-DOWN
MODES
COMMENTS
0
X
X
X
All OFF except serial bus and registers
OFF
SHDN mode
(which retain values). A zero on the SHDN
OFF
OFF
OFF
OFF
1
0
X
X
pin overrides the SHDN bit.
ON
1
1
0
0
All OFF except RF PLL, RF VCO, serial
bus, and registers (which retain values).
ON
OFF
X
X
OFF
IDLE mode
RF PLL and RF VCO are on or off
1
1
0
1
depending on the control-bit values
before toggling the IDLE pin to zero.
ON
OFF
X
X
X
1
1
1
X
Power-up mode
The 5 different TX blocks can be toggled
ON/OFF using the serial bus.
ON
X
X
X
X
10
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